littlefield
Junior Member level 3
there is a fifo design which the clock of data input is running at 100mhz,while the clock of data output is running at 80mhz. The input data is a fix pattern . 800 input clocks carry in 800 data continuously,and the other 200 clocks carry in no data.how big the fifo should be in order to avoid data over/under_run?please select the minimum depth below to meet the requirement.
A.160 B.200 C.800 D.1000
my answer is A. Is it right?
A.160 B.200 C.800 D.1000
my answer is A. Is it right?